Processor-based systems such as computers and embedded devices commonly use memory devices including random access memory (RAM) devices. For example, high-performance very large scale integration (VLSI) systems generally employ large amounts of on-die SRAM for cache functions. Static RAM, or SRAM, stores data in a flip-flop that usually includes four to six transistors. As scaling of such technologies continues, particular attention is given to the performance of the SRAM as well as its die size.
Since a SRAM cell supports both read and write operations, its performance may be measured by its read stability and its write margin. The performance criteria coupled with the need to maintain a small cell area are particularly challenging for any new SRAM design. The read stability and the write margin typically make conflicting demands on the SRAM cell. During a read operation, the SRAM cell preferably has “weak disturbance” at the internal storage nodes in order to avoid being erroneously flipped (from a “1” state to a “0” state, and vice-versa). This is preferred whether a “true read,” in which the contents of the cell are sent to read/write circuitry, or a so-called “dummy read,” in which the read is not actually processed, takes place. On the other hand, during a write operation, a SRAM cell preferably has “strong disturbance” in order to successfully flip the cell. Thus, read stability depends on weak disturbance within the SRAM cell while write margin depends on strong disturbance within the same SRAM cell.
The apparent paradox between read and write requirements has made SRAM cell scaling difficult, and thus cell scaling is typically limited by both the read and write operations. Accordingly, it is desirable to have an SRAM memory cell that can meet both read and write stability requirements.